Resume

(Here’s a summary of my CV, please contact me for more details)

Education

University of Florida – Gainesville, FL

Ph.D., Computer Engineering (Expected: Summer, 2017)

Case Western Reserve University – Cleveland, OH

M.S., Computer Engineering (Fall, 2015)
Thesis: “Event Detection Algorithm for Single-Sensor Bladder Pressure Data”
Committee: S. Bhunia (chair), M.S. Damaser, F. Merat

B.S.E., Computer Engineering (Spring, 2012)

Experience

Cleveland VA Medical Center – Biomedical Engineer
Advanced Platform Technology Center · Cleveland, OH · 08/2012 ~ present

University of Florida – Research Assistant
Florida Institute for Cyber Security (FICS) · Gainesville, FL · 08/2015 ~ present

Case Western Reserve University – Research Assistant
Nanoscape Research Lab · Cleveland, OH · 09/2010 ~ 08/2015

EZShred LLC – Student Software Developer
Chesterland, OH · 05/2009 ~ 08/2011

Awards & Achievements

  • Winner of Best Paper Award, IEEE Biomedical Circuits and Systems Conference (BioCAS), Shanghai, China, 2016.
  • Recipient of NSF Award for Young Professionals Contributing to Smart and Connected Health, IEEE Engineering in Medicine and Biology Conference (EMBC), Orlando, FL, 2016.
  • Winner, Attributes of a Gator Engineer Award for Professional Excellence. University of Florida, Gainesville, FL, 2016.
  • A. Richard Newton Young Student Fellow. ACM Design Automation Conference (DAC), San Francisco, CA, 2014.
  • Winner (2nd Place), Apps for Energy, US Department of Energy, Washington DC, 2012.

Professional Memberships

  • Student Member: IEEE, IEEE EMBS, IEEE CAS
  • Student Member: ACM, ACM SIGDA
  • Student Member: Semiconductor Research Corporation (SRC/GRC)

Skills

Software

  • Matlab – Signal/Image Processing, algorithm development
  • C#.NET – General Purpose, WPF,  WinForms, XNA (UI design, XML layouts, 2D/3D graphics)
  • Java – Desktop, Android (mostly mobile phone/tablet side projects), Lucene
  • C, MIPS & PIC assembly

Hardware

  • Verilog, Quartus II & Altera FPGAs, ModelSim, Nios II soft processor system
  • Design Compiler and SoC Encounter
  • Spice, ADK (DAIC & IC Station) experience

Languages
English (Fluent), French (Conversational), Arabic (Spoken, Conversational)

Publications

(Alternatively, see my Google Scholar profile, which may be more up-to-date.)

Journal

  • Stitt, G. Karam, R. Yang, K. Bhunia, S. “A Uniquified Virtualization Approach to Hardware Security”. To Appear: IEEE Embedded Systems Letters (ESL), 2017.
  • Karam, R. Paul, S. Puri, R. Bhunia, S. “Memory-Centric Reconfigurable Accelerator for Classification and Machine Learning Applications”. To Appear: ACM Journal on Emerging Technologies in Computing Systems (JETC), 2017.
  • Mal-Sarkar, S. Karam, R. Krishna, Aswin. Bhunia, S. “Design and Validation for FPGA Trust under Hardware Trojan Attacks”. In: IEEE Transactions on Multi-Scale Computer Systems (TMSCS), 2016.
  • Qian, W. Babecki, C. Karam, R. Bhunia, S. “ENFIRE: A Spatio-temporal Fine-grained Reconfigurable Hardware”. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016.
  • Qian, W. Chen, P.Y. Karam, R. Gao, L. Bhunia, S. Yu, S. “Energy-Efficient Adaptive Computing with Multifunctional Memory”. In: Transactions on Circuits and Systems (TCAS) II, 2016.
  • Karam, R. Puri, R. Bhunia, S. “Energy-Efficient Adaptive Hardware Accelerator for Text Mining Application Kernels”. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016.
  • Babecki, C.  Qian, W. Paul, S. Karam, R. Bhunia, S. “An Embedded Memory-Centric Reconfigurable Hardware Accelerator for Security Applications”. In: IEEE Transactions on Computing, 2015.
  • Karam, R. Bourbeau, D. Majerus, S. Makovey, I. Goldman, H. B. Damaser, M. S. Bhunia, S. “Real-Time Classification of Bladder Events for Effective Diagnosis and Treatment of Urinary Incontinence”. In: IEEE Transactions on Biomedical Engineering, 2015.
  • Karam, R. Puri, R. Ghosh, S. Bhunia, S. “Emerging Trends in Design and Applications of Memory based Computing and Content Addressable Memories”. In: Proceedings of the IEEE, 2015.
  • Paul, S. Krishna, A. Qian, W. Karam, R. Bhunia, S. “MAHA: An Energy-Efficient Malleable Hardware Accelerator for Data-Intensive Applications”. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014.

Conference Papers & Abstracts

  • Karam, R. Hoque, T. Ray, S. Tehranipoor, M. Bhunia, S. “Robust Bitstream Protection in FPGA-based Systems through Low-Overhead Obfuscation”. To Appear: 2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig).
  • Karam, R. Hoque, T. Ray, S. Tehranipoor, M. Bhunia, S. “MUTARCH: Architectural Diversity for FPGA Device and IP Security”. To Appear: 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 2017.
  • Shomaji, S. Basak, A. Mandal, S. Karam, R. Bhunia, S. “A Wearable Ultrasound Assembly for Early Detection of Cardiovascular Diseases”. To Appear: IEEE Healthcare Innovations & Point-of-Care Tchnologies (HI-POCT), 2016.
  • Karam, R. Majerus, S. Bourbeau, D. Damaser, M. S. Bhunia, S. “Ultralow-power Data Compression for Implantable Bladder Pressure Monitor: Algorithm and Hardware Implementation”. To Appear: IEEE Biomedical Circuits and Systems Conference (BioCAS), 2016. [Best Paper Award Winner]
  • Hoque, T. Karam, R. Bhunia, S. “Protection of IPs mapped to FPGA against Malicious Hardware”. SRC TECHCON, 2016.
  • Karam, R. Paul, S. Puri, R. Bhunia, S. “Energy-Efficient Reconfigurable Accelerator for Data Intensive Analytics”. SRC TECHCON, 2016.
  • Karam, R. Bhunia, S. Majerus, S. Brose, S. W. Damaser, M. S. Bourbeau, D. “Real-time, Autonomous Bladder Event Classification and Closed-Loop Control from Single-Channel Pressure Data”. To Appear: 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2016.
  • Karam, R. Majerus, S. Bhunia, S. Brose, S.W. Damaser, M.S. Bourbeau, D. “Autonomous closed-loop genital nerve stimulation identifies and inhibits hyper-reflexic bladder contractions”. [Abstract] In: Engineering and Urology Society Annual Meeting, 2016.
  • Qian, W. Babecki, C. Karam, R. Bhunia, S. “ENFIRE: An Energy-efficient Fine-grained Spatio-temporal Reconfigurable Computing Fabric”. [Abstract] In: Proceedings of the 24th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. ACM, 2016.
  • Wang, P. Majerus, S. Karam, R. Bhunia, S. Hanzlicek, B. Lin, D. Zhu, H. Anderson, J. Damaser, M. Zorman, C. Ko, W. “Long-Term Evaluation of a Non-Hermetic Micropackage Technology for MEMS-Based, Implantable Pressure Sensors”. In: 18th International Solid-State Sensors, Actuators and Microsystems Conference (TRANSDUCERS), 2015.
  • Makovey, I. Karam, R. Majerus, S. Bourbeau, D. Zhu, H. Bhunia, S. Damaser, M. S. “Event Detection Algorithm in Single Channel Bladder Pressure Recording”. [Abstract] In: Engineering and Urology Society Annual Meeting, 2015.
  • Makovey, I. Majerus, S. Karam, R. Hanzlicek, B. Streicher, M. Zhu, H. Damaser, M. S. “Wireless Implantable Rechargeable Bladder Pressure Sensor: Cystoscopic Implantation and Ambulatory Data Collection”. [Abstract] In: Annual Meeting of American Urological Society, 2015.
  • Karam, R. Bourbeau, D. Majerus, S. Makovey, I. Goldman, H. B. Damaser, M. S. Bhunia, S. “Real-time contraction event detection from bladder pressure recordings for effective diagnosis and treatment of urinary incontinence”. In: Innovating for Continence: The Engineering Challenge, 2015.
  • Qian, W. Karam, R. Bhunia, S. “Trade-off between energy and quality of service through dynamic operand truncation and fusion”. In: Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI. ACM, pp. 79–80, 2014.

Invited Papers

  • Karam, R. Liu, R. Chen, P.-Y. Yu, S. Bhunia, S. “Security Primitive Design with Nanoscale Devices: A Case Study with Resistive RAM”, In: Proceedings of the 26th edition on Great Lakes Symposium on VLSI. ACM, 2016. [Invited paper in special session on Emerging Technology Devices for Security].
  • Karam, R. Yang, K. Bhunia, S. “Energy-Efficient Reconfigurable Computing Using Spintronic Memory”. In: Proceedings of the 58th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS). [Invited paper in special session on Emerging Nanoelectronic Logic and Memory Devices based Circuits and Architectures].
  • Paul, S. Karam, R. Bhunia, S. Puri, R. “Energy-Efficient Hardware Acceleration Through Computing in the Memory”. In: Proceedings of the conference on Design, Automation & Test in Europe. European Design and Automation Association. [Invited paper in special session on Memcomputing: the Cape of Good Hope].

Presentations

(This is a list of presentations, including invited talks and conference lectures.)

  • Robert Karam, Somnath Paul, Ruchir Puri, and Swarup Bhunia. “Energy-Efficient Reconfigurable Accelerator for Data Intensive Analytics”. Presented in SRC TECHCON in session on Beyond von Neumann Architectures, September 2016.
  • Swarup Bhunia, Robert Karam. “Malleable Memory-Centric Hardware Accelerator Using RRAM for Data-Intensive Applications: Device-Circuit-System Co-Design Approach”. Co-presented in SRC/GRC e-Workshop, August 2016.
  • Robert Karam, Swarup Bhunia. Steve Majerus,  Steven W. Brose, Margot S. Damaser, and Dennis Bourbeau. “Real-time Autonomous Bladder Event Classification and Closed-Loop Control from Single-Channel Pressure Data”. 38th Annual IEEE Engineering in Medicine and Biology Conference (EMBC), August 2016. [Lecture Presentation in session on Diagnostic Systems and Technologies]
  • Robert Karam, Rui Liu, Pai-Yu Chen, Shimeng Yu, and Swarup Bhunia. “Security Primitive Design with Nanoscale Devices: A Case Study with Resistive RAM”, 26th edition on Great Lakes Symposium on VLSI (GLSVLSI), May 2016 [Invited, presented in special session on Emerging Technology Devices for Security]
  • Robert Karam, Kai Yang, and Swarup Bhunia. “Energy-Efficient Reconfigurable Computing Using Spintronic Memory”. 58th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS). [Invited, presented in special session on Emerging Nanoelectronic Logic and Memory Devices based Circuits and Architectures]
  • Robert Karam and Swarup Bhunia. “Memory-Centric Adaptive Accelerator for Data-Intensive Kernels”, IBM T.J. Watson Research Lab, Yorktown Heights, New York, USA, May 2015. [Invited presentation in IBM CMOS Forum]
  • Somnath Paul, Saibal Mukhopadhyay, and Swarup Bhunia, “Robust Low-Power Reconfigurable Computing with a Variation-Aware Preferential Design Approach”, IEEE International Conference on Integrated Circuit Design and Technology (ICICDT), 2014. [Invited, presented by Robert Karam in session on Design Methodologies for Memory and Circuit Reliability]